Topological DAG Visualization
No active gate to display.
1
Educational Context
Phase 1: Setup & Inputs
Welcome to the Garbled Circuit Simulator. Alice and Bob define the boolean circuit.
Live Data:
Alice's Wires: wA3, wA2, wA1, wA0
Bob's Wires: wB3, wB2, wB1, wB0
Values are set in the Control Panel. The keys haven't been generated yet.
You can toggle optimizations:
- Free XOR: XOR gates are evaluated using only XOR operations without cryptography.
- Row Reduction: Reduces garbled tables from 4 rows to 3 rows.
- Point-and-Permute: Uses pointer bits to evaluate without trial decryption.